US 11,940,836 B2
Dual chip clock synchronization
Hagen Schmidt, Tuebingen (DE); Andreas H. A. Arp, Nufringen (DE); and Daniel Kiss, Stuttgart (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Mar. 31, 2022, as Appl. No. 17/657,520.
Prior Publication US 2023/0317127 A1, Oct. 5, 2023
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
setting a first clock of a first semiconductor circuit and a second clock of a second semiconductor circuit to a common clock source when both the first and second semiconductor circuits are in a slow clock speed, wherein an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating at the slow clock speed;
synchronizing a first division counter of the first clock and a second division counter of the second clock at the slow clock speed; and
simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, wherein the IO is not capable of operating at the fast clock speed.