CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01)] | 20 Claims |
1. A method comprising:
setting a first clock of a first semiconductor circuit and a second clock of a second semiconductor circuit to a common clock source when both the first and second semiconductor circuits are in a slow clock speed, wherein an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating at the slow clock speed;
synchronizing a first division counter of the first clock and a second division counter of the second clock at the slow clock speed; and
simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, wherein the IO is not capable of operating at the fast clock speed.
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