US 11,940,834 B1
Methods and devices for fault tolerant quantum gates
Naomi Nickerson, San Francisco, CA (US); Hector Bombin Palomo, Kyoto (JP); and Benjamin Brown, Palo Alto, CA (US)
Assigned to Psiquantum, Corp., Palo Alto, CA (US)
Filed by Psiquantum, Corp., Palo Alto, CA (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,955.
Application 17/894,955 is a continuation of application No. 16/509,219, filed on Jul. 11, 2019, granted, now 11,460,876.
Claims priority of provisional application 62/772,587, filed on Nov. 28, 2018.
Claims priority of provisional application 62/696,846, filed on Jul. 11, 2018.
This patent is subject to a terminal disclaimer.
Int. Cl. G06E 3/00 (2006.01); G06N 10/00 (2022.01)
CPC G06E 3/005 (2013.01) [G06N 10/00 (2019.01)] 10 Claims
OG exemplary drawing
 
1. A method, comprising:
obtaining a plurality of entangled qubits, wherein:
a first subset of the plurality of entangled qubits defines a first plane;
a second subset of the plurality of entangled qubits, that is distinct from, mutually exclusive to, and adjacent to, the first subset of the plurality of entangled qubits, defines a second plane that is parallel to and offset from the first plane; and
the plurality of entangled qubits includes a defect qubit that is entangled with at least one qubit on the first plane and at least one qubit on the second plane.