US 11,940,495 B1
Built in self-test of heterogeneous integrated radio frequency chiplets
James Buckwalter, Santa Barbara, CA (US); Michael Hodge, Huntersville, NC (US); Justin Kim, San Jose, CA (US); Daniel Green, McLean, VA (US); and Florian Herrault, Agoura Hills, CA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Jul. 13, 2023, as Appl. No. 18/352,164.
Application 18/352,164 is a division of application No. 18/190,559, filed on Mar. 27, 2023, granted, now 11,733,297.
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01)
CPC G01R 31/3187 (2013.01) [G01R 31/31704 (2013.01); G01R 31/318511 (2013.01); G01R 31/318513 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method of forming an electronic assembly having built-in self-test of chiplets, the method comprising:
bonding a host wafer having a first circuit including a plurality of wafer transistors and a plurality of wafer passive, non-transistor devices to an encapsulation layer;
bonding a plurality of chiplets having a second circuit including at least one radio frequency (RF) chiplet transistor to the encapsulation layer;
forming electrical interconnects between the chiplets and wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit; and
forming a plurality of oscillators each having some of the plurality of wafer transistors, the at least one RF chiplet transistor of a chiplet and some of the electrical interconnects, wherein each oscillator of the plurality of oscillators produces a signal for the built-in self-test circuit for testing an assembly design of the electronic assembly and a speed of the at least one RF chiplet transistor of the chiplet.