US 11,940,493 B1
Flexible one-hot decoding logic for clock controls
Mahmut Yilmaz, Los Altos Hills, CA (US); Vinod Pagalone, San Jose, CA (US); Munish Aggarwal, Santa Clara, CA (US); and Doochul Shin, Sunnyvale, CA (US)
Assigned to NVIDIA CORP., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Sep. 16, 2022, as Appl. No. 17/932,808.
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/318536 (2013.01) [G01R 31/31727 (2013.01); G01R 31/318597 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A circuit comprising:
a plurality of scan registers;
a decoder configured to translate a combined output of the scan registers into a plurality of one-hot controls;
local clock gates in a plurality of different clock domains coupled to receive the one-hot control si a first of the local clock gates in a first clock domain coupled to receive one of the one-hot controls;
an inverter configured at a clock domain crossing from the first clock domain to a second clock domain; and
a second of the local clock gates in the second clock domain coupled to receive an inverted version of the one of the one-hot controls from the inverter.