CPC G01R 31/318536 (2013.01) [G01R 31/31727 (2013.01); G01R 31/318597 (2013.01)] | 17 Claims |
1. A circuit comprising:
a plurality of scan registers;
a decoder configured to translate a combined output of the scan registers into a plurality of one-hot controls;
local clock gates in a plurality of different clock domains coupled to receive the one-hot control si a first of the local clock gates in a first clock domain coupled to receive one of the one-hot controls;
an inverter configured at a clock domain crossing from the first clock domain to a second clock domain; and
a second of the local clock gates in the second clock domain coupled to receive an inverted version of the one of the one-hot controls from the inverter.
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