US 11,940,491 B2
Built-in self-test for die-to-die physical interfaces
Fabien S. Faure, Santa Clara, CA (US); Arnaud J. Forestier, San Diego, CA (US); and Vikram Mehta, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 19, 2023, as Appl. No. 18/303,401.
Application 18/303,401 is a continuation of application No. 17/320,165, filed on May 13, 2021, granted, now 11,662,380.
Prior Publication US 2023/0384377 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G01R 31/319 (2006.01); G01R 31/66 (2020.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31713 (2013.01); G01R 31/31725 (2013.01); G01R 31/2889 (2013.01); G01R 31/31712 (2013.01); G01R 31/31715 (2013.01); G01R 31/31716 (2013.01); G01R 31/31723 (2013.01); G01R 31/318572 (2013.01); G01R 31/31926 (2013.01); G01R 31/66 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a particular integrated circuit, included in a particular chip package, including:
a particular interface circuit that includes a first set transmit pins and a first set of receive pins;
a particular set of switch circuits configured to couple, when enabled, one or more of the first set of receive pins to a corresponding one or more of the first set of transmit pins; and
a particular test circuit configured to enable, based on a particular mapping that is associated with a first test mode, a first subset of switch circuits of the particular set of switch circuits, coupling a first subset of the first set of receive pins to a first subset of the first set of transmit pins;
wherein the first subset of switch circuits is further configured to route a test packet, received via the first subset of receive pins, to the first subset of transmit pins, the routing bypassing the particular test circuit; and
wherein the particular test circuit is further configured to enable, based on a different mapping determined based on a second test mode, a second subset of switch circuits of the particular set of switch circuits, coupling a second subset of the first set of receive pins to a second subset of the first set of transmit pins.