US 11,940,490 B2
Interleaved testing of digital and analog subsystems with on-chip testing interface
Praveen Raghuraman, Chennai (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 18, 2022, as Appl. No. 17/990,607.
Application 17/990,607 is a division of application No. 16/983,938, filed on Aug. 3, 2020, granted, now 11,531,061.
Prior Publication US 2023/0078568 A1, Mar. 16, 2023
Int. Cl. G01R 31/317 (2006.01); G01R 31/3167 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/31718 (2013.01) [G01R 31/3167 (2013.01); G01R 31/31724 (2013.01); G01R 31/3177 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of interleaved on-chip testing, comprising:
merging a test setup for analog components and digital components; and
interleaving execution of the digital components and the analog components with the test setup to achieve concurrency via a unified mode of operation, the interleaving execution comprising performing a memory write operation while waiting for a phase locked loop (PLL) to lock.