CPC G01R 31/31718 (2013.01) [G01R 31/3167 (2013.01); G01R 31/31724 (2013.01); G01R 31/3177 (2013.01)] | 6 Claims |
1. A method of interleaved on-chip testing, comprising:
merging a test setup for analog components and digital components; and
interleaving execution of the digital components and the analog components with the test setup to achieve concurrency via a unified mode of operation, the interleaving execution comprising performing a memory write operation while waiting for a phase locked loop (PLL) to lock.
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