US 11,940,483 B2
Systems, methods and devices for high-speed input/output margin testing
Sam J. Strickling, Portland, OR (US); Daniel S. Froelich, Portland, OR (US); Michelle L Baldwin, Mount Juliet, TN (US); Jonathan San, Palo Alto, CA (US); and Lin-Yung Chen, New Taipei (TW)
Assigned to Tektronix, Inc., Beaverton, OR (US)
Filed by Tektronix, Inc., Beaverton, OR (US)
Filed on Sep. 9, 2021, as Appl. No. 17/470,424.
Application 17/470,424 is a continuation in part of application No. 16/778,249, filed on Jan. 31, 2020.
Application 16/778,249 is a continuation in part of application No. 16/778,262, filed on Jan. 31, 2020.
Claims priority of provisional application 63/111,533, filed on Nov. 9, 2020.
Claims priority of provisional application 62/804,942, filed on Feb. 13, 2019.
Claims priority of provisional application 62/799,720, filed on Jan. 31, 2019.
Prior Publication US 2021/0405108 A1, Dec. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G06F 11/273 (2006.01); G06F 13/20 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 30/398 (2020.01); H04L 43/50 (2022.01)
CPC G01R 31/2815 (2013.01) [G01R 31/2808 (2013.01); G01R 31/2818 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A test system, comprising:
a margin tester including a plurality of interfaces for electrical connection to external devices, wherein at least one interface of the margin tester is configured to connect to a removable test fixture, the test fixture being external to the margin tester and configured to connect to a device under test (DUT);
the margin tester having:
one or more lanes connected to the at least one interface; and
a controller coupled to the at least one interface through the one or more lanes, wherein the controller is configured to establish a single-lane or multi-lane high speed input/output (I/O) link with the DUT via the test fixture, in which, for one or more lanes of the single-lane or multi-lane high speed I/O link, the controller implements physical and logical link layers that communicatively connect the margin tester with the DUT via the at least one interface and the test fixture, and to cause the margin tester to assess an electrical margin of the single-lane or multi-lane high speed I/O link in either or both transmit (Tx) and receive (Rx) directions.