US 11,939,625 B2
Method and sensor for detecting L-cystine
Zhong Cao, Changsha (CN); Jia Yang, Changsha (CN); Chen Liu, Changsha (CN); Zhongliang Xiao, Changsha (CN); Dan Li, Changsha (CN); Ling Zhang, Changsha (CN); Yuyang Zhang, Changsha (CN); and Jiaxin Li, Changsha (CN)
Assigned to CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY, Changsha (CN)
Appl. No. 17/258,932
Filed by CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY, Changsha (CN)
PCT Filed Aug. 24, 2019, PCT No. PCT/CN2019/102372
§ 371(c)(1), (2) Date Jan. 8, 2021,
PCT Pub. No. WO2020/043026, PCT Pub. Date Mar. 5, 2020.
Claims priority of application No. 201810984084.5 (CN), filed on Aug. 28, 2018; and application No. 201821387669.0 (CN), filed on Aug. 28, 2018.
Prior Publication US 2021/0123093 A1, Apr. 29, 2021
Int. Cl. C12Q 1/6809 (2018.01); G01N 27/26 (2006.01)
CPC C12Q 1/6809 (2013.01) [G01N 27/26 (2013.01); C12Q 2500/00 (2013.01); C12Q 2545/10 (2013.01); C12Q 2560/00 (2013.01); C12Q 2565/607 (2013.01)] 12 Claims
 
1. A method for detecting L-cystine, comprising steps:
step (1): implanting a p-well in an N-type substrate, wherein the N-type substrate is arranged on a Si substrate layer of a field effect transistor (FET), constructing a source electrode and a drain electrode at the p-well by thermal evaporation and magnetron sputtering techniques to obtain a processed Si substrate layer, wherein the processed Si substrate layer is provided with the p-well in the N-type substrate, the source electrode and the source electrode, constructing a SiO2 layer on the processed Si substrate layer, plating an Al—Cu alloy layer, a Cr—Pd alloy layer and an Au membrane layer sequentially on a substrate layer of a polysilicon gate electrode by the thermal evaporation and magnetron sputtering techniques, finally constructing a silicon nitride layer on the substrate layer of the polysilicon gate electrode and the SiO2 layer, and extending the polysilicon gate electrode by 0.1-500 mm to obtain an extended gate FET (EGFET) with a gold-gate electrode (GGE);
step (2): preparing an ethanol solution of sodium 3,3′-dithiodipropane sulfonate (SPS), immersing a cleaned GGE of the EGFET in the ethanol solution of the SPS, allowing to stand still at 25° C. to obtain an immersed GGE, and then washing the immersed GGE to obtain an SPS membrane-modified GGE/SPS; and
step (3): connecting a reference electrode and the SPS membrane-modified GGE/SPS to an electrode connector of the EGFET to form a differential amplifier circuit with two high-impedance ends; inserting the reference electrode and the SPS membrane-modified GGE/SPS into a phosphate-buffered solution (PBS); connecting power connectors of the EGFET to a positive electrode and a negative electrode of a regulated power supply respectively, and connecting a signal output connector of the EGFET to a test port of a multimeter to form a sensing loop; wherein a potential change of the sensing loop is sensitively detected based on an FET in-situ signal amplification; a potential of the SPS membrane-modified GGE/SPS in the PBS tends to stabilize gradually with time, and the SPS membrane-modified GGE/SPS is used as a working electrode; when the potential of the SPS membrane-modified GGE/SPS is stable, adding test samples containing different concentrations of the L-cystine to obtain corresponding potential response data to achieve detection of the L-cystine in the test samples.