US 11,939,216 B2
Method with stealth dicing process for fabricating MEMS semiconductor chips
Andre Brockmeier, Villach (AT); Stephan Helbig, Regensburg (DE); and Adolf Koller, Regensburg (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 1, 2021, as Appl. No. 17/188,082.
Claims priority of application No. 102020109149.4 (DE), filed on Apr. 2, 2020.
Prior Publication US 2021/0309513 A1, Oct. 7, 2021
Int. Cl. B81C 1/00 (2006.01); G02B 26/08 (2006.01); G02B 26/10 (2006.01)
CPC B81C 1/00904 (2013.01) [B81C 1/00888 (2013.01); G02B 26/0833 (2013.01); G02B 26/105 (2013.01); B81B 2201/042 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/0143 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method, comprising:
producing a semiconductor wafer, the semiconductor wafer comprising:
a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the plurality of MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer,
a first semiconductor material layer arranged at the first main surface, and
a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer;
removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips; and
applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.