US 11,937,520 B2
Integrating circuit elements in a stacked quantum computing device
Julian Shaw Kelly, Santa Barbara, CA (US); and Joshua Yousouf Mutus, Santa Barbara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Nov. 18, 2022, as Appl. No. 17/989,833.
Application 17/989,833 is a continuation of application No. 17/178,853, filed on Feb. 18, 2021, granted, now 11,508,781.
Application 17/178,853 is a continuation of application No. 16/487,555, granted, now 10,950,654, issued on Mar. 16, 2021, previously published as PCT/US2017/065668, filed on Dec. 12, 2017.
Claims priority of provisional application 62/470,670, filed on Mar. 13, 2017.
Prior Publication US 2023/0084122 A1, Mar. 16, 2023
Int. Cl. H10N 69/00 (2023.01); G06N 10/00 (2022.01); H01L 25/065 (2023.01)
CPC H10N 69/00 (2023.02) [G06N 10/00 (2019.01); H01L 25/0657 (2013.01); H01L 2225/06513 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first chip comprising a qubit; and
a second chip bonded to the first chip, the second chip comprising a readout device,
wherein the readout device comprises a first readout element at a first end of the readout device and comprises a second readout element at a second end of the readout device, wherein the first readout element directly overlaps the qubit, and wherein the second readout element is laterally displaced from the qubit without directly overlapping the qubit.