US 11,937,030 B2
Optical link system and method for computation
Patrick Gallagher, Menlo Park, CA (US); Thomas W. Baehr-Jones, Menlo Park, CA (US); Michael Gao, Menlo Park, CA (US); and Mitchell A. Nahmias, Menlo Park, CA (US)
Assigned to Luminous Computing, Inc., , CA (US)
Filed by Luminous Computing, Inc., Menlo Park, CA (US)
Filed on Sep. 27, 2022, as Appl. No. 17/953,590.
Application 17/953,590 is a continuation of application No. 17/337,289, filed on Jun. 2, 2021, granted, now 11,490,177.
Claims priority of provisional application 63/187,812, filed on May 12, 2021.
Claims priority of provisional application 63/035,667, filed on Jun. 5, 2020.
Prior Publication US 2023/0016616 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04Q 11/00 (2006.01); H04B 10/25 (2013.01)
CPC H04Q 11/0005 (2013.01) [H04B 10/25 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An optical link system, comprising:
a photonics substrate;
a plurality of optical links, each optical link of the plurality of optical links comprising:
an optical waveguide defined on the photonics substrate;
a first optoelectronic transducer optically coupled to the optical waveguide; and
a second optoelectronic transducer optically coupled to the optical waveguide; and
a plurality of processing modules, each processing module of the plurality of processing modules comprising:
a respective electronics substrate mounted on the photonics substrate; and
a respective processor integrated circuit (IC) defined on the respective electronics substrate, each respective processor IC communicatively connected to other processing modules of the plurality of processing modules via respective optical links of the plurality of optical links, wherein each first optoelectronic transducer of the respective optical links is connected to the respective processor IC;
wherein the plurality of optical links communicatively couple each processing module of the plurality of processing modules directly to a plurality of other processing modules of the plurality of processing modules; and
wherein:
the plurality of processing modules define a rectangular array comprising a plurality of rows and a plurality of columns;
each row of the plurality of rows comprises a respective subset of at least three processing modules of the plurality of processing modules, wherein, for each row, each processing module of the row is communicatively connected directly to every other processing module of the row via a respective optical link of the plurality of optical links; and
each column of the plurality of columns comprises a respective subset of at least three processing modules of the plurality of processing modules, wherein, for each column, each processing module of the column is communicatively connected directly to every other processing module of the column via a respective optical link of the plurality of optical links.