US 11,935,756 B2
Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
Baosuo Zhou, Boise, ID (US); Mirzafer K. Abatchev, Fremont, CA (US); Ardavan Niroomand, Boise, ID (US); Paul A. Morgan, Kuna, ID (US); Shuang Meng, Austin, TX (US); Joseph Neil Greeley, Boise, ID (US); and Brian J. Coppa, Tempe, AZ (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,478.
Application 14/507,507 is a division of application No. 11/484,271, filed on Jul. 10, 2006, granted, now 8,852,851, issued on Oct. 7, 2014.
Application 17/730,478 is a continuation of application No. 16/807,002, filed on Mar. 2, 2020, granted, now 11,335,563.
Application 16/807,002 is a continuation of application No. 15/993,568, filed on May 30, 2018, granted, now 10,607,844, issued on Mar. 31, 2020.
Application 15/993,568 is a continuation of application No. 15/681,066, filed on Aug. 18, 2017, granted, now 10,096,483, issued on Oct. 9, 2018.
Application 15/681,066 is a continuation of application No. 15/076,474, filed on Mar. 21, 2016, granted, now 9,761,457, issued on Sep. 12, 2017.
Application 15/076,474 is a continuation of application No. 14/507,507, filed on Oct. 6, 2014, granted, now 9,305,782, issued on Apr. 5, 2016.
Prior Publication US 2022/0254644 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/306 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/30625 (2013.01) [H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/30604 (2013.01); H01L 21/3086 (2013.01); H01L 21/3088 (2013.01); H01L 23/564 (2013.01); H01L 2924/0002 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method used during fabrication of a semiconductor device, comprising:
providing a layer to be etched;
forming a sacrificial patterning layer over the layer to be etched, wherein the sacrificial patterning layer comprises a plurality of segmented portions having at least first and second cross sectional sidewalls;
forming a plurality of sacrificial first spacers, with one spacer formed on each sidewall of each segmented portion of the sacrificial patterning layer;
removing the sacrificial patterning layer;
forming a conformal second spacer layer over the plurality of sacrificial first spacers;
removing a portion of the conformal second spacer layer to form a plurality of second spacers on the sacrificial first spacers, wherein the second spacers have different elevational thicknesses;
subsequent to forming the second spacers, removing the sacrificial first spacers; and
etching the layer to be etched using the second spacers as a pattern.