US 11,935,740 B2
Dual gate dielectric layers grown with an inhibitor layer
Mark Francis Arendt, Richardson, TX (US); and Damien Thomas Gilmore, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Apr. 27, 2022, as Appl. No. 17/730,944.
Application 17/730,944 is a division of application No. 16/836,755, filed on Mar. 31, 2020, granted, now 11,348,782.
Prior Publication US 2022/0254627 A1, Aug. 11, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01)
CPC H01L 21/02164 (2013.01) [H01L 21/02271 (2013.01); H01L 21/823462 (2013.01); H01L 29/51 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a semiconductor material;
a first dielectric layer on the semiconductor material, the first dielectric layer including an oxidized inhibitor layer and an oxidized semiconductor material layer located between the oxidized inhibitor layer and the substrate, the first dielectric layer having a first thickness; and
a second dielectric layer on the semiconductor material, the second dielectric layer having a second thickness,
wherein:
the second thickness is greater than the first thickness; and
the second dielectric layer extends further into the semiconductor material than the first dielectric layer.