US 11,935,603 B2
Erase power loss indicator (EPLI) implementation in flash memory device
Amichai Givant, Rosh Ha'Ayin (IL); Idan Koren, Kiryat Ono (IL); Shivananda Shetty, San Jose, CA (US); Pawan Singh, San Jose, CA (US); Yoram Betser, Mazkeret Batya (IL); Kobi Danon, Te-Aviv (IL); and Amir Rochman, Tel-aviv (IL)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Jan. 11, 2022, as Appl. No. 17/572,881.
Claims priority of provisional application 63/275,779, filed on Nov. 4, 2021.
Prior Publication US 2023/0137469 A1, May 4, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/344 (2013.01) [G11C 16/0425 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory, comprising:
an array of non-volatile memory cells arranged in rows to be selected by word lines and columns to be selected, for writing and reading;
a plurality of reference word lines comprising first reference word lines and second reference word lines, each to select corresponding supplemental non-volatile memory cells from the first reference word line and reference non-volatile cells from the second reference word line;
a plurality of sense amplifiers arranged to:
read, using a comparison of the supplemental non-volatile memory cells of the first reference word lines to the reference non-volatile memory cells of the second reference word lines, system data that has been written to the supplemental non-volatile memory cells of the first reference word lines after an erase operation; and
a processing element to determine a status of the erase operation of the non-volatile memory, based on reading the system data that has been written to the supplemental non-volatile memory cells of the first reference word lines.