US 11,934,964 B2
Finite automata global counter in a data flow graph-driven analytics platform having analytics hardware accelerators
Rajan Goyal, Saratoga, CA (US); and Satyanarayana Lakshmipathi Billa, Sunnyvale, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 20, 2020, as Appl. No. 16/825,714.
Prior Publication US 2021/0295181 A1, Sep. 23, 2021
Int. Cl. G06F 17/00 (2019.01); G06F 7/00 (2006.01); G06F 16/2455 (2019.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01)
CPC G06N 5/04 (2013.01) [G06F 16/24568 (2019.01); G06N 20/00 (2019.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a memory including a finite automata (FA) graph, wherein the FA graph includes a plurality of nodes connected by directional arcs, wherein:
each arc representing transitions between nodes of the FA graph based on criteria specified for the respective arc,
the plurality of nodes including a skip node and a root node;
the directional arcs include an arc from the skip node to the root node; and
one or more hardware-based regular expression (RegEx) accelerators connected to the memory, wherein each RegEx accelerator includes a regular expression engine, the regular expression engine configured to receive the FA graph from the memory and to perform a regular expression operation on a stream of data units based on the received FA graph by initially traversing the root node,
wherein the regular expression engine is further configured to, a to reaching the skip node, consume a predefined number of data units in the stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload.