US 11,934,760 B1
Voltage impacts on delays for timing simulation
Joao Geada, Chelmsford, MA (US); and Nicholas Lee Rethman, North Andover, MA (US)
Assigned to ANSYS, INC., Canonsburg, PA (US)
Filed by ANSYS, INC., Canonsburg, PA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/645,882.
Int. Cl. G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/367 (2020.01) [G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/38 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine readable medium storing executable program instructions which when executed by a processing system cause the processing system to perform a method, the method comprising:
receiving a design of circuit;
computing a first effective resistance between a first voltage supply pin of an instance in the circuit and a first set of one or more power supply sources in the circuit containing the instance;
adding the first effective resistance into the design to determine timing delay when only the instance switches;
determining a minimum timing delay for the instance based on the added first effective resistance.