| CPC G06F 13/4239 (2013.01) [G06F 12/0246 (2013.01); G06F 13/1615 (2013.01); G06F 13/4068 (2013.01)] | 20 Claims |
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1. An interface between a host and a multi-plane flash memory, comprising:
a first storage unit configured to receive and store a first plane pipeline command issued from the host, and output the first plane pipeline command to a first plane of the flash memory;
a second storage unit configured to receive and store a second plane pipeline command issued from the host, and output the second plane pipeline command to a second plane of the flash memory; and
a controller electrically connected to the first storage unit and the second storage unit, and configured to output the first plane pipeline command to the first plane and the second plane pipeline command to the second plane synchronously only when no read process is performed on any one of the first plane and the second plane of the flash memory, the first plane pipeline command and the second plane pipeline command being stored in the first storage unit and the second storage unit, respectively, so that the first plane of the flash memory performs a first operation corresponding to the first plane pipeline command and the second plane of the flash memory performs a second operation corresponding to the second plane pipeline command synchronously in response to a signal that indicates data stored in the first plane and the second plane have been cached into a first cache and a second cache, respectively, and the first cache and the second cache are ready to be accessed by the host,
wherein the first plane pipeline command is distinct from the second plane pipeline command.
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