CPC G06F 12/0831 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/109 (2013.01); G06F 12/128 (2013.01); G06F 13/161 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01); G06F 15/17368 (2013.01); G06F 15/7807 (2013.01); G06F 2212/305 (2013.01); G06F 2212/657 (2013.01)] | 21 Claims |
1. A system, comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
a plurality of memory controller circuits configured to interface with a system memory; and
an interconnect fabric configured to provide communication between the memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
wherein the processor cores, the graphics processing units, the peripheral devices and the memory controller circuits are configured to communicate via a unified memory architecture in which a given page within a unified address space defined by the unified memory architecture is distributed among the plurality of memory controller circuits; and
wherein the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.
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