US 11,934,252 B2
Shallow hibernate power state
Deping He, Boise, ID (US); Nadav Grosz, Broomfield, CO (US); and Jonathan S. Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2022, as Appl. No. 17/648,394.
Claims priority of provisional application 63/162,140, filed on Mar. 17, 2021.
Prior Publication US 2022/0300061 A1, Sep. 22, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3287 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array;
a controller coupled with the memory array, the controller configurable to cause the apparatus to:
read a value from a register while operating in a first power state;
disable a first timer based at least in part on reading the value from the register;
transition from the first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components associated with the memory array;
initiate a second timer based at least in part on transitioning from the first power state to the second power state;
determine the second timer satisfies a threshold based at least in part on initiating the second timer, wherein the threshold is configurable based at least in part on a power performance target of the apparatus or a link target of the apparatus; and
transition, based at least in part on determining the second timer satisfies the threshold, from the second power state to a third power state having a third current lower than the second current.