US 11,934,219 B2
Integrated functional and design for testability (DFT) clock delivery architecture
Arvind Jain, San Diego, CA (US); Divya Gangadharan, San Diego, CA (US); Muhammad Nasir, San Diego, CA (US); Hong Dai, San Diego, CA (US); and Madan Krishnappa, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,621.
Prior Publication US 2023/0315141 A1, Oct. 5, 2023
Int. Cl. G06F 1/06 (2006.01); G01R 31/317 (2006.01); H04B 1/401 (2015.01)
CPC G06F 1/06 (2013.01) [G01R 31/31727 (2013.01); H04B 1/401 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively, wherein the first set of TCCs comprises:
a first set of clock inputs configured to receive a set of at-speed clocks, respectively,
a second set of clock inputs configured to receive a first shift test clock, and
a first set of functional/test interfaces configured to receive control signals indicating a mode of operation, respectively; and
a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.