US 11,930,715 B2
Highly physical etch resistive photoresist mask to define large height sub 30nm via and metal hard mask for MRAM devices
Yi Yang, Fremont, CA (US); Dongna Shen, San Jose, CA (US); and Yu-Jen Wang, San Jose, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., HsinChu (TW)
Filed on Jan. 4, 2021, as Appl. No. 17/140,790.
Application 17/140,790 is a continuation of application No. 16/133,955, filed on Sep. 18, 2018, granted, now 10,886,461.
Prior Publication US 2021/0151668 A1, May 20, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/01 (2023.02) [H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a conductive via on a bottom electrode;
encapsulating the conductive via with a first dielectric layer;
forming a stack of magnetic tunneling junction (MTJ) layers on the conductive via;
forming a top electrode on the stack of MTJ layers; and
patterning the stack of MTJ layers and the first dielectric layer using the top electrode as a mask such that metal re-deposition material is formed on sidewalls of the patterned first dielectric layer, wherein the metal re-deposition material is prevented from interfacing with the conductive via by the patterned first dielectric layer being disposed on sidewalls of the conductive via.