US 11,930,696 B2
Fabrication method of a double-gate carbon nanotube transistor
Jin Cai, Hsinchu (TW); and Sheng-Kai Su, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 5, 2021, as Appl. No. 17/308,635.
Claims priority of provisional application 63/162,672, filed on Mar. 18, 2021.
Prior Publication US 2022/0302389 A1, Sep. 22, 2022
Int. Cl. H10K 85/20 (2023.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H10K 10/46 (2023.01)
CPC H10K 85/221 (2023.02) [H01L 21/02606 (2013.01); H01L 29/0673 (2013.01); H10K 10/472 (2023.02); H10K 10/474 (2023.02); H10K 10/484 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing an isolation layer over a substrate;
depositing an etch stop layer over the isolation layer;
depositing a dielectric layer over the etch stop layer;
forming carbon nanotubes on the dielectric layer;
forming a dummy gate stack on the carbon nanotubes;
forming gate spacers on opposing sides of the dummy gate stack;
removing the dummy gate stack to form a trench between the gate spacers, wherein the carbon nanotubes are exposed to the trench;
etching a portion of the dielectric layer underlying the carbon nanotubes, wherein the etching the portion of the dielectric layer is stopped on the etch stop layer, and wherein the carbon nanotubes are suspended;
forming a replacement gate dielectric surrounding the carbon nanotubes; and
forming a gate electrode surrounding the replacement gate dielectric.