US 11,930,643 B2
Thin film transistor deck selection in a memory device
Daniele Vimercati, El Dorado Hills, CA (US); and Fatma Arzum Simsek-Ege, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 21, 2021, as Appl. No. 17/327,031.
Prior Publication US 2022/0375951 A1, Nov. 24, 2022
Int. Cl. H10B 53/30 (2023.01); G11C 11/22 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 53/20 (2023.01); H10B 53/40 (2023.01)
CPC H10B 53/30 (2023.02) [G11C 11/2255 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10B 53/20 (2023.02); H10B 53/40 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a column decoder of a memory die;
a first memory array at a first level above a substrate of the memory die, the first memory array comprising a first plurality of digit lines each operable to couple with the column decoder based at least in part on activating a respective first transistor at the first level; and
a second memory array at a second level above the substrate of the memory die, the second memory array comprising a second plurality of digit lines each operable to couple with the column decoder based at least in part on activating a respective second transistor at the second level.