US 11,929,927 B2
Network interface for data transport in heterogeneous computing environments
Pratik M. Marolia, Hillsboro, OR (US); Rajesh M. Sankaran, Portland, OR (US); Ashok Raj, Portland, OR (US); Nrupal Jani, Hillsboro, OR (US); Parthasarathy Sarangam, Portland, OR (US); and Robert O. Sharp, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2020, as Appl. No. 17/129,756.
Application 17/129,756 is a division of application No. 16/435,328, filed on Jun. 7, 2019, granted, now 11,025,544.
Prior Publication US 2021/0112003 A1, Apr. 15, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/28 (2006.01); G06F 12/1081 (2016.01); H04L 45/60 (2022.01); H04L 45/74 (2022.01); H04L 49/90 (2022.01)
CPC H04L 45/742 (2013.01) [G06F 12/1081 (2013.01); G06F 13/28 (2013.01); H04L 45/60 (2013.01); H04L 49/9068 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A system comprising:
a central processing unit (CPU) interconnect; and
a network interface device comprising:
a first interface;
a second interface;
direct memory access (DMA) circuitry; and
circuitry to:
based on receipt of a packet:
copy a portion of the received packet via the first interface to the CPU interconnect to forward to a first memory buffer accessible by a CPU connected to the CPU interconnect and
based on receipt of a second packet:
copy, by the DMA circuitry, a portion of the second received packet via the second interface to an accelerator fabric to forward to a second memory buffer accessible by an accelerator device connected to the accelerator fabric, wherein
the accelerator device comprises a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC) and
the network interface device comprises second circuitry to: based on a request to transmit a third packet that comprises data generated by the accelerator device, copy the data via the second interface and the accelerator fabric and cause transmission of the third packet.