US 11,929,761 B1
Low latency decoder
Bengt Anders Ulriksson, Longmont, CO (US)
Assigned to Seagate Technology LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Oct. 7, 2022, as Appl. No. 17/938,854.
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1131 (2013.01) [H03M 13/1125 (2013.01); H03M 13/6577 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a low density parity check (LDPC) decoder configured decode a codeword of bits, including:
a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to an edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword;
the edge combiner configured to:
generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors;
provide the plurality of output message vectors to the plurality of check node vectors simultaneously;
a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and
a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.