	US 11,929,437 B2
	Semiconductor device comprising various thin-film transistors
Shunpei Yamazaki, Setagaya (JP); Daisuke Matsubayashi, Atsugi (JP); and Keisuke Murayama, Chigasaki (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Oct. 13, 2021, as Appl. No. 17/500,020.
Application 17/500,020 is a continuation of application No. 17/065,635, filed on Oct. 8, 2020, granted, now 11,355,645.
Application 17/065,635 is a continuation of application No. 16/707,432, filed on Dec. 9, 2019, granted, now 10,872,981, issued on Dec. 22, 2020.
Application 16/707,432 is a continuation of application No. 16/180,210, filed on Nov. 5, 2018, granted, now 10,559,699, issued on Feb. 11, 2020.
Application 16/180,210 is a continuation of application No. 15/262,547, filed on Sep. 12, 2016, granted, now 10,158,026, issued on Dec. 18, 2018.
Application 15/262,547 is a continuation of application No. 14/594,991, filed on Jan. 12, 2015, granted, now 9,472,679, issued on Oct. 18, 2016.
Application 14/594,991 is a continuation of application No. 13/860,792, filed on Apr. 11, 2013, granted, now 8,946,702, issued on Feb. 3, 2015.
Claims priority of application No. 2012-091539 (JP), filed on Apr. 13, 2012.
Prior Publication US 2022/0037373 A1, Feb. 3, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/7869 (2013.01) [H01L 29/7831 (2013.01)]

6 Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first layer comprising silicon over a substrate;

a first insulating layer over the first layer;

a first gate electrode of the third transistor over the first insulating layer;

a first conductive layer over the first gate electrode of the third transistor, the first conductive layer functioning as a first gate electrode of the second transistor;

a second insulating layer over the first conductive layer;

a second layer comprising an oxide semiconductor over the second insulating layer;

a third insulating layer over the second layer;

a second conductive layer over the third insulating layer, the second conductive layer functioning as a second gate electrode of the second transistor; and

a third conductive layer in contact with a top surface of the second layer,

wherein the second transistor comprises the oxide semiconductor in a channel formation region,

wherein a first wiring is electrically connected to one of a source electrode and a drain electrode of the first transistor,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,

wherein a second wiring is electrically connected to a first gate electrode of the first transistor,

wherein a third wiring is electrically connected to the first gate electrode of the second transistor,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor and one of a source electrode and a drain electrode of the fourth transistor,

wherein the first transistor comprises a second gate electrode overlapping with the first gate electrode of the first transistor, and

wherein the third conductive layer comprises a region extending below the second layer.