US 11,929,428 B2
Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
Thomas J. Smith, Jr., Raleigh, NC (US); Saptharishi Sriram, Cary, NC (US); and Charles W. Richards, IV, Cary, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by CREE, INC., Durham, NC (US)
Filed on May 17, 2021, as Appl. No. 17/321,992.
Prior Publication US 2022/0367696 A1, Nov. 17, 2022
Int. Cl. H02H 3/06 (2006.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H02H 3/12 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 21/7605 (2013.01); H01L 21/765 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/66462 (2013.01); H02H 3/06 (2013.01); H02H 3/12 (2013.01)] 64 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate;
a group III-Nitride barrier layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate on the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer;
a p-region being arranged at or below the group III-Nitride barrier layer;
a recovery enhancement circuit configured to reduce an impact of an overload received by the gate; and
a group III-Nitride buffer layer on the substrate,
wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain; and
wherein the group III-Nitride barrier layer is arranged on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer.