US 11,929,412 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP); Masami Jintyou, Tochigi (JP); Takahiro Iguchi, Tochigi (JP); Yukinori Shima, Gunma (JP); and Kenichi Okazaki, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jul. 18, 2022, as Appl. No. 17/866,822.
Application 17/866,822 is a continuation of application No. 16/758,091, granted, now 11,424,334, previously published as PCT/IB2018/058226, filed on Oct. 23, 2018.
Claims priority of application No. 2017-213017 (JP), filed on Nov. 2, 2017.
Prior Publication US 2022/0359691 A1, Nov. 10, 2022
Int. Cl. H01L 27/12 (2006.01); G02F 1/1368 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/42364 (2013.01) [G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
a semiconductor layer over the second insulating layer;
a third insulating layer over the semiconductor layer;
a first gate electrode over the third insulating layer;
a fourth insulating layer over the first gate electrode;
a first conductive layer functioning as one of a source and a drain of a transistor and being electrically connected to the semiconductor layer; and
a second conductive layer functioning as the other of the source and the drain of the transistor and being electrically connected to the semiconductor layer,
wherein, in a cross-sectional view in a channel width direction, an entire top surface of the second insulating layer is covered by a bottom surface of the fourth insulating layer, a bottom surface of the semiconductor layer, and a bottom surface of the third insulating layer.