US 11,929,408 B2
Layout techniques and optimization for power transistors
Shamit Som, Chelmsford, MA (US); Wayne Mack Struble, Franklin, MA (US); Jason Matthew Barrett, Amherst, NH (US); Nishant R Yamujala, Somerville, MA (US); and John Stephen Atherton, Acton, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on May 14, 2020, as Appl. No. 16/874,098.
Prior Publication US 2021/0359092 A1, Nov. 18, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/41758 (2013.01) [H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field effect transistor, comprising:
a first source metal;
a second source metal;
a gate manifold comprising a gate manifold body, a first angled gate tab, and a second angled gate tab; and
a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor, wherein the drain metal comprises a drain metal body having a notched region between the first source metal and the second source metal over the channel, the notched region defining a first projecting portion and a second projecting portion of the drain metal body, the first projecting portion and the second projecting portion positioned on respective sides of the notched region.