US 11,929,364 B2
Parasitic capacitance reduction in GaN devices
Gabriel R. Cueva, Bedford, NH (US); Timothy E. Boles, Tyngsboro, MA (US); and Wayne Mack Struble, Franklin, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Sep. 20, 2021, as Appl. No. 17/479,543.
Application 17/479,543 is a continuation of application No. 16/000,287, filed on Jun. 5, 2018, granted, now 11,158,575.
Prior Publication US 2022/0005764 A1, Jan. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/06 (2006.01); H01L 21/02 (2006.01); H01L 21/74 (2006.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/8252 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/66 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01)
CPC H01L 27/0605 (2013.01) [H01L 21/0254 (2013.01); H01L 21/743 (2013.01); H01L 21/746 (2013.01); H01L 21/7605 (2013.01); H01L 21/76202 (2013.01); H01L 21/8252 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H01L 23/66 (2013.01); H01L 29/0649 (2013.01); H01L 29/2003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a low dielectric constant material region in the substrate, the low dielectric constant material region comprising an oxide and being positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure, a dielectric constant of the low dielectric constant material region being lower than a dielectric constant of the substrate;
a III-nitride material layer over the substrate, the III-nitride material layer extending over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area;
a first device formed in the III-nitride material layer in the first device area;
a second device in the III-nitride material layer in the second device area; and
an interconnect formed over the low dielectric constant material region, the interconnect comprising a metal interconnect line that provides a continuous conductive path of metal from the first device area, over the low dielectric constant material region, and to the second device area.