US 11,929,362 B2
Semiconductor integrated circuit device having an electrostatic discharge protection circuit and method of manufacturing the semiconductor integrated circuit device
Joung Cheul Choi, Daejeon (KR); and Jae Young You, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 23, 2021, as Appl. No. 17/534,182.
Application 17/534,182 is a division of application No. 16/230,598, filed on Dec. 21, 2018, granted, now 11,201,145.
Claims priority of application No. 10-2018-0066735 (KR), filed on Jun. 11, 2018.
Prior Publication US 2022/0085008 A1, Mar. 17, 2022
Int. Cl. H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/735 (2006.01)
CPC H01L 27/0259 (2013.01) [H01L 29/0821 (2013.01); H01L 29/6625 (2013.01); H01L 29/735 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor integrated circuit device, the method comprising:
providing a semiconductor substrate having a first conductivity type;
forming a body contact region in the semiconductor substrate, the body contact region including first impurities having the first conductivity type;
forming isolation layers in the semiconductor substrate;
implanting second impurities with a second conductivity type opposite to the first conductivity type to the semiconductor substrate, thereby forming a first well which is spaced from the body contact region and a second well which contacts with a sidewall of the body contact region; and
forming a base and an emitter in the first well between the isolation layers and forming a collector in the body contact region,
wherein the first well and the second well are formed to have a same depth.