US 11,929,352 B2
Semiconductor memory device having transistors between bonding pads and word lines
Hiroshi Maejima, Tokyo (JP); Toshifumi Hashimoto, Fujisawa Kanagawa (JP); Takashi Maeda, Kamakura Kanagawa (JP); Masumi Saitoh, Yokohama Kanagawa (JP); and Tetsuaki Utsumi, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 10, 2022, as Appl. No. 17/984,959.
Application 17/984,959 is a continuation of application No. 16/802,462, filed on Feb. 26, 2020, granted, now 11,538,791.
Claims priority of application No. 2019-111045 (JP), filed on Jun. 14, 2019.
Prior Publication US 2023/0074030 A1, Mar. 9, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory chip comprising:
a set of first word lines, which are stacked along a first direction and extend in a first region and a second region of the memory chip along a second direction crossing the first direction;
a pillar including:
a semiconductor layer extending through the first word lines along the first direction in the first region, and
an insulating layer between the semiconductor layer and the first word lines;
a set of memory cells in the first region, each of which is disposed at a corresponding intersection of the pillar and one of the first word lines;
a set of bonding pads in the second region; and
a set of transistors in the second region, each of which is configured to electrically connect or disconnect a corresponding one of the first word lines to or from a corresponding one of the bonding pads, wherein
a number of bonding pads in the set of bonding pads is smaller than a number of transistors in the set of transistors.