US 11,929,339 B2
Innovative interconnect design for package architecture to improve latency
Md Altaf Hossain, Portland, OR (US); Ankireddy Nalamalpu, Portland, OR (US); and Dheeraj Subbareddy, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 13, 2023, as Appl. No. 18/300,329.
Application 18/300,329 is a continuation of application No. 17/466,396, filed on Sep. 3, 2021, granted, now 11,658,144.
Application 17/466,396 is a continuation of application No. 16/023,846, filed on Jun. 29, 2018, granted, now 11,121,109, issued on Sep. 12, 2021.
Claims priority of provisional application 62/577,581, filed on Oct. 26, 2017.
Prior Publication US 2023/0352431 A1, Nov. 2, 2023
Int. Cl. G06F 13/38 (2006.01); G06F 13/14 (2006.01); G06F 13/42 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/18 (2013.01) [G06F 13/14 (2013.01); G06F 13/385 (2013.01); G06F 13/4221 (2013.01); G06F 13/4265 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
an interposer comprising a first electrical trace and a second electrical trace;
a first die, coupled to the interposer, comprising a first plurality of package bumps; and
a second die, coupled to the interposer, comprising a second plurality of package bumps, wherein the first plurality of package bumps has a first closest pitch between package bumps of the first plurality of package bumps and the second plurality of package bumps has a second closest pitch between package bumps of the second plurality of package bumps, the first closest pitch is shorter than the second closest pitch, the first electrical trace couples a first package bump of the first plurality of package bumps with a second package bump of the second plurality of package bumps, and the second electrical trace couples a third package bump of the first plurality of package bumps with a fourth package bump of the second plurality of package bumps.