US 11,929,336 B2
Semiconductor device including resistor element
Chan Ho Yoon, Icheon-si (KR)
Assigned to SK hynix inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 12, 2022, as Appl. No. 17/887,385.
Application 17/887,385 is a continuation of application No. 17/007,059, filed on Aug. 31, 2020, granted, now 11,450,636.
Claims priority of application No. 10-2020-0046620 (KR), filed on Apr. 17, 2020.
Prior Publication US 2022/0392860 A1, Dec. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 23/5228 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19104 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first pad defined on one surface of a first chip, the first chip includes a memory cell array disposed in a cell region and a first peripheral circuit disposed in a peripheral region outside of the cell region;
a second pad defined on one surface of a second chip, which is stacked on the first chip in a first direction, and bonded to the first pad, the second chip includes a second peripheral circuit disposed in the peripheral region;
a first horizontal resistor pattern defined on the one surface of the first chip and coupled to the first pad; and
a second horizontal resistor pattern defined on the one surface of the second chip and coupled to the second pad,
wherein the first horizontal resistor pattern and the second horizontal resistor pattern are disposed between the first peripheral circuit and the second peripheral circuit in the peripheral region,
wherein the first horizontal resistor pattern and the second horizontal resistor pattern do not overlap with each other in the first direction.