US 11,929,322 B2
Method of forming device and package structure
Hsien-Wei Chen, Hsinchu (TW); An-Jhih Su, Taoyuan (TW); and Li-Hsien Huang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/871,998.
Application 17/871,998 is a division of application No. 16/923,118, filed on Jul. 8, 2020, granted, now 11,444,021.
Application 16/923,118 is a continuation of application No. 16/147,897, filed on Oct. 1, 2018, granted, now 10,741,490, issued on Aug. 11, 2020.
Application 16/147,897 is a continuation of application No. 14/724,817, filed on May 29, 2015, granted, now 10,090,241, issued on Oct. 2, 2018.
Prior Publication US 2022/0359383 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/311 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/311 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a package structure, comprising:
forming a dielectric layer over a carrier;
providing a die and forming a conductive structure on the dielectric layer and beside the die;
forming an encapsulant surrounding the die and covering the conductive structure;
debonding the carrier and exposing the dielectric layer overlying the conductive structure;
laser drilling an opening in the dielectric layer to expose a first area of a top surface of the conductive structure; and
widening the opening by an etching process to expose a second area of the top surface of the conductive structure, wherein the first area is smaller than the second area.