US 11,929,313 B2
Chip package structure and method for manufacturing the same, and module
Mingyu Wang, Shanghai (CN); Kerui Xi, Shanghai (CN); Xuhui Peng, Shanghai (CN); Feng Qin, Shanghai (CN); and Jie Zhang, Shanghai (CN)
Assigned to Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai (CN)
Filed by Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai (CN)
Filed on Nov. 22, 2021, as Appl. No. 17/532,248.
Claims priority of application No. 202110732782.8 (CN), filed on Jun. 30, 2021.
Prior Publication US 2022/0084923 A1, Mar. 17, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/32 (2006.01); H01L 31/02 (2006.01); H04N 23/54 (2023.01)
CPC H01L 23/49816 (2013.01) [H01L 23/15 (2013.01); H01L 23/32 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 31/02002 (2013.01); H04N 23/54 (2023.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a substrate comprising a first region and a second region surrounding the first region;
a wiring layer located on a side of the substrate and comprising at least one metal wire, wherein at least part of a metal wire of the at least one metal wire is in contact with the substrate, and wherein the at least one metal wire overlaps with the second region in a direction perpendicular to the substrate;
a chip located on a side of the wiring layer facing away from the substrate, wherein the chip corresponds to the first region, wherein the chip comprises a first conductive bump disposed on a side of the chip facing towards to the substrate, and wherein the first conductive bump is electrically connected to one of the at least one metal wire; and
a second conductive bump electrically connected to one of the at least one metal wire, wherein the second conductive bump does not overlap with the chip in the direction perpendicular to the substrate;
wherein the chip comprises a photosensitive region located at the side of the chip facing towards the substrate and opposite to the first region, and wherein the photosensitive region does not overlap with the metal wire in the wiring layer.