	US 11,929,289 B2
	Semiconductor device having work-function metal and method of forming the same
Juyoun Kim, Hwasung-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 3, 2022, as Appl. No. 17/958,805.
Application 15/468,631 is a division of application No. 14/972,704, filed on Dec. 17, 2015, granted, now 9,627,500, issued on Apr. 18, 2017.
Application 17/958,805 is a continuation of application No. 17/335,174, filed on Jun. 1, 2021, granted, now 11,462,442, issued on Oct. 4, 2022.
Application 17/335,174 is a continuation of application No. 16/921,037, filed on Jul. 6, 2020, granted, now 11,043,430, issued on Jun. 22, 2021.
Application 16/921,037 is a continuation of application No. 16/459,889, filed on Jul. 2, 2019, granted, now 10,734,288, issued on Aug. 4, 2020.
Application 16/459,889 is a continuation of application No. 15/468,631, filed on Mar. 24, 2017, granted, now 10,388,574, issued on Aug. 20, 2019.
Claims priority of application No. 10-2015-0014418 (KR), filed on Jan. 29, 2015.
Prior Publication US 2023/0029263 A1, Jan. 26, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)

CPC H01L 21/823821 (2013.01) [H01L 21/28088 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/845 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01)]

20 Claims

1. A semiconductor device comprising:

a substrate;

a first fin active area and a second fin active area on the substrate;

a first gate dielectric layer on the first fin active area;

a first gate electrode on the first gate dielectric layer, the first gate electrode including

a first layer on the first gate dielectric and including TiN,

a second layer on the first layer and including TiAlC and TiN,

a third layer on the second layer and including TiN, and

a fourth layer on the third layer and including W;

a first spacer on a sidewall of the first gate dielectric layer and the first gate electrode;

a second gate dielectric layer on the second fin active area;

a second gate electrode on the second gate dielectric layer, the second gate electrode including

a fifth layer on the second gate dielectric layer and including TiAlC and TiN,

a sixth layer on the fifth layer and including TiN, and

a seventh layer on the sixth layer and including W;

a second spacer on a sidewall of the second gate dielectric layer and the second gate electrode; and

wherein a second width of the seventh layer is greater than a first width of the fourth layer,

wherein upper surfaces of the first gate dielectric layer, the first gate electrode, and the first spacer are coplanar, and

wherein upper surfaces of the second gate dielectric layer, the second gate electrode, and the second spacer are coplanar.