CPC G11C 7/16 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); H03M 1/1245 (2013.01)] | 17 Claims |
1. A memory circuit comprising:
a memory array comprising a plurality of memory cells;
an analog-to-digital converter (ADC) comprising:
a first m-bit sub-ADC; and
a first n-bit sub-ADC, wherein n does not equal m; and
a control circuit coupled to the memory array, the control circuit configured to:
determine a workload sparsity level;
based on the workload sparsity level, determine a bit-precision requirement; and
based on the bit-precision requirement, activate the first m-bit sub-ADC, the first n-bit sub-ADC, or both.
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