US 11,929,134 B2
Indicating a status of a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 17, 2022, as Appl. No. 17/807,625.
Prior Publication US 2023/0410933 A1, Dec. 21, 2023
Int. Cl. G11C 29/12 (2006.01); G11C 7/10 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 7/1009 (2013.01); G11C 29/12005 (2013.01); G11C 29/4401 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device;
identify, based on the one or more bits, that the memory built-in self-test is enabled;
set a data mask inversion (DMI) bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled,
wherein the DMI bit of the memory device indicates a status of the memory built-in self-test while the memory built-in self-test is enabled, and indicates a status of a data masking function or a data inversion function of the memory device while the memory built-in self-test is disabled; and
set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.