US 11,929,133 B2
Methods for recovery for memory systems and memory systems employing the same
Rachael Skreen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 7, 2022, as Appl. No. 17/571,319.
Prior Publication US 2023/0223094 A1, Jul. 13, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller;
a plurality of memory devices operably connected to the controller;
circuitry configured to measure a performance metric for each memory device of the plurality; and
circuitry configured to select, based upon the measured performance metric, a subset of the memory devices of the plurality to disable in response to a recovery command.