US 11,929,126 B2
Memory device and operating method of the memory device
Sung Hyun Hwang, Icheon-si (KR); Jae Yeop Jung, Icheon-si (KR); and Se Chun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 18, 2022, as Appl. No. 17/675,925.
Claims priority of application No. 10-2021-0130339 (KR), filed on Sep. 30, 2021.
Prior Publication US 2023/0108946 A1, Apr. 6, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block in which a plurality of cell pages are coupled to each of word lines;
a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page; and
a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting the time point at which the verify voltage is output.