US 11,929,122 B2
Apparatus and method for erasing data in a non-volatile memory device
Tae Heui Kwon, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 14, 2022, as Appl. No. 17/671,002.
Claims priority of application No. 10-2021-0093236 (KR), filed on Jul. 16, 2021.
Prior Publication US 2023/0017178 A1, Jan. 19, 2023
Int. Cl. G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3445 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a cell string including plural non-volatile memory cells which are capable of storing data, the cell string arranged between a bit line and a source line;
plural first discharge transistors coupled in parallel to the source line for providing a first current path of discharging the charges;
at least one second discharge transistor coupled to the bit line for providing a second current path of discharging charges which are accumulated in a channel formed through the cell string; and
a control circuit configured to control the plural first discharge transistors and the at least one second discharge transistor for synchronizing discharge of the charges via the first and second current paths, the bit line, and the source line during an erase operation for erasing the data stored in the plural non-volatile memory cells.