CPC G11C 11/4099 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns;
access circuitry configured to:
generate a power supply reference voltage level of the array on a power supply connection used by memory bit cells of one or more columns of the plurality of the columns; and
in response to receiving a reset request:
generate, on the power supply connection, a given voltage level that is less than a threshold voltage of transistors used in the memory bit cell; and
assert a write word line of each row of the plurality of rows.
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