US 11,929,114 B2
Rapid tag invalidation circuit
Russell Schreiber, Austin, TX (US); and Kyle David Whittle, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2021, as Appl. No. 17/564,680.
Prior Publication US 2023/0206995 A1, Jun. 29, 2023
Int. Cl. G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01)
CPC G11C 11/4099 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns;
access circuitry configured to:
generate a power supply reference voltage level of the array on a power supply connection used by memory bit cells of one or more columns of the plurality of the columns; and
in response to receiving a reset request:
generate, on the power supply connection, a given voltage level that is less than a threshold voltage of transistors used in the memory bit cell; and
assert a write word line of each row of the plurality of rows.