US 11,928,474 B2
Selectively updating branch predictors for loops executed from loop buffers in a processor
Rami Mohammad Al Sheikh, Morrisville, NC (US); Saransh Jain, Raleigh, NC (US); Michael Scott McIlvaine, Raleigh, NC (US); and Daren Eugene Streett, Cary, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 3, 2022, as Appl. No. 17/832,350.
Prior Publication US 2023/0393853 A1, Dec. 7, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/32 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/325 (2013.01); G06F 9/381 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A method, comprising:
detecting a loop comprising a plurality of loop instructions among a plurality of instructions in an instruction stream;
determining that the loop is stored within a loop buffer circuit;
determining a count of potential history register updates to a history register for the plurality of loop instructions;
determining whether the count of potential history register updates exceeds a size of the history register; and
responsive to determining that the count of potential history register updates does not exceed the size of the history register, updating a branch predictor of a branch predictor circuit based on the plurality of loop instructions.