US 11,928,468 B2
Systems and methods for improved mapping of computational loops on reconfigurable architectures
Mahesh Balasubramanian, Tempe, AZ (US); and Aviral Shrivastava, Phoenix, AZ (US)
Assigned to ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, Tempe, AZ (US)
Filed by Mahesh Balasubramanian, Tempe, AZ (US); and Aviral Shrivastava, Phoenix, AZ (US)
Filed on Nov. 23, 2021, as Appl. No. 17/533,663.
Claims priority of provisional application 63/117,684, filed on Nov. 24, 2020.
Prior Publication US 2022/0164189 A1, May 26, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/445 (2018.01)
CPC G06F 9/30065 (2013.01) [G06F 9/3001 (2013.01); G06F 9/44505 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor in communication with a memory and a coarse-grained reconfigurable architecture (CGRA) unit, the memory including instructions, which when executed, cause the processor to:
generate a data flow graph expressive of a computational loop configured for execution on the CGRA unit, wherein the data flow graph includes a plurality of nodes;
determine an upper bound modulo timeslot for each node in the data flow graph, the upper bound modulo timeslot being representative of an upper scheduling bound of a CGRA schedule for each node of the plurality of nodes; and
iteratively generate a random schedule for population within the CGRA schedule that schedules each node of the data flow graph to a random timeslot between a lower bound modulo timeslot and the upper bound modulo timeslot of the CGRA schedule with respect to an initiation interval value.