US 11,928,445 B2
Compiler for a fracturable data path in a reconfigurable data processor
Raghu Prabhakar, San Jose, CA (US); David Brian Jackson, Dana Point, CA (US); and Scott Burson, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,214.
Claims priority of provisional application 63/301,465, filed on Jan. 20, 2022.
Prior Publication US 2023/0229407 A1, Jul. 20, 2023
Int. Cl. G06F 9/44 (2018.01); G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 15/80 (2006.01)
CPC G06F 8/441 (2013.01) [G06F 9/3001 (2013.01); G06F 9/44505 (2013.01); G06F 15/80 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable medium comprising computer instructions that, in response to being executed by a processor, cause the processor to:
produce a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the first address calculation associated with a first operation of a plurality of independent operations of the configurable unit and the second address calculation associated with a second operation of the plurality of independent operations of the configurable unit, the fracturable data path of the configurable unit comprising a plurality of computation stages respectively including a pipeline register, the configuration file produced by:
analyzing the first address calculation and the second address calculation;
assigning a first set of stages of the plurality of computation stages to the first operation to generate the first address sequence using the first set of stages based on said analysis;
assigning a second set of stages of the plurality of computation stages to the second operation to generate the second address sequence using the second set of stages based on said analysis; and
including two or more immediate values for each computation stage of the first set of stages and second set of stages in the configuration file.