US 11,928,353 B2
Multi-page parity data storage in a memory device
Harish R Singidi, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Vamsi Pavan Rayaprolu, Santa Clara, CA (US); and Kishore Kumar Muchherla, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 18, 2023, as Appl. No. 18/098,279.
Application 18/098,279 is a continuation of application No. 17/002,374, filed on Aug. 25, 2020, granted, now 11,561,722.
Prior Publication US 2023/0153011 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01); H03M 7/30 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0679 (2013.01); G06F 11/1004 (2013.01); H03M 7/6011 (2013.01)] 20 Claims
OG exemplary drawing
 
9. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
creating a parity page for stored in a page of a plurality of pages of a data unit of a memory device;
associating the parity page with parity data associated with the data unit;
responsive to determining that the plurality of pages of the data unit satisfies a first condition, compressing the parity data; and
responsive to determining that a size of the compressed parity data satisfies a second condition, releasing at least a subset of the parity data corresponding to a subset of the data that is free from defects.