US 11,928,347 B2
Managing voltage bin selection for blocks of a memory device
Kishore Kumar Muchherla, Fremont, CA (US); Mustafa N Kaynak, San Diego, CA (US); Peter Feeley, Boise, ID (US); Sampath K Ratnam, Boise, ID (US); Shane Nowell, Boise, ID (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Karl D Schuh, Santa Cruz, CA (US); and Jiangang Wu, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 27, 2023, as Appl. No. 18/114,967.
Application 18/114,967 is a continuation of application No. 17/219,489, filed on Mar. 31, 2021, granted, now 11,593,005.
Prior Publication US 2023/0205438 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 16/26 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
sorting a plurality of blocks of the memory device;
identifying, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block;
identifying, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and
responsive to determining that the first voltage bin matches the second voltage bin, assigning the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.