US 11,928,333 B2
Reset verification in a memory system
Scott E. Schaefer, Boise, ID (US); and Aaron P. Boehm, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,183.
Application 17/946,183 is a continuation of application No. 17/097,766, filed on Nov. 13, 2020, granted, now 11,474,698.
Claims priority of provisional application 62/943,722, filed on Dec. 4, 2019.
Prior Publication US 2023/0014955 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 7/20 (2006.01); G11C 11/4072 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 7/20 (2013.01); G11C 11/4072 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
performing a reset operation at a memory device;
determining, based at least in part on performing the reset operation, whether to set a mode register to a first value indicating a successful execution of the reset operation or to a second value indicating an error associated with executing the reset operation;
setting the mode register to the second value based at least in part on detecting the error associated with executing the reset operation; and
transmitting, to a host device after setting the mode register to the second value, an indication that the reset operation is unsuccessful based at least in part on the second value.