US 11,928,077 B2
Data processing circuit, data storage device including the same, and operating method thereof
Kyoung Lae Cho, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 5, 2021, as Appl. No. 17/193,135.
Application 17/193,135 is a continuation of application No. 14/873,975, filed on Oct. 2, 2015.
Claims priority of application No. 10-2015-0076165 (KR), filed on May 29, 2015.
Prior Publication US 2021/0191899 A1, Jun. 24, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 16/00 (2019.01); G06F 16/11 (2019.01); G06F 16/28 (2019.01)
CPC G06F 16/116 (2019.01) [G06F 16/285 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a controller comprising:
a processor configured to control a read or write operation based on a command received from an external device; and
a data processing circuit configured to randomize a plurality of input bit groups to output output bits including a transformed input bit group based on a seed received from the processor and a polynomial; and
a nonvolatile memory configured to write the output bits at a memory region according to an address offset,
wherein the seed has a relationship to the address offset and the polynomial has a degree which is an integral multiple of a total number of input bits in the input bit groups provided tothe data processing circuit and the seed corresponding to each memory region having relationship to the address offset is fixed.